1. Field of the Invention
This invention relates to a method of forming an alignment mark, and more particularly to a method used in tungsten chemical mechanical polishing (WCMP) process to achieve a better alignment performance.
2. Description of Related Art
As the integration of a semiconductor device increases, the distance between interconnect lines is necessarily reduced and consequently the line width is also accordingly reduced. When the line width is reduced down to about 0.18 microns at a level of deep sub-half micron, a conventional planarization method of spin-on glass (SOG) technology is no longer suitable. Instead, a chemical mechanical polishing (CMP) technology is proposed to perform a global planarization and thereby plays a necessary role for very-large scale integrated (VLSI) fabrications. In particular, the WCMP process must become a necessary process in ultra-large semiconductor integration (ULSI) fabrications in the near future. However, the CMP process has a problem of alignment error, because as CMP process is applied to planarize the device elements on a semiconductor substrate, an alignment mark pattern may be smeared by planarization. This causes a difficulty in the alignment of photo-masks and results in alignment error, which consequently induces a pattern transfer error in subsequent fabrications. This alignment error is more obvious for fabrications including a tungsten (W) layer that are planarized by WCMP.
FIGS. 1A-1E are cross-sectional views schematically illustrating a convention fabrication flow of an alignment mark formed on the zero layer, according to a proposal from ASML company. In FIG. 1A, an alignment mark pattern 102 including a trench 104 with a depth of about 1200 .ANG. is first formed on a semiconductor substrate 100 at an alignment mark region. The substrate 100 also includes a device element region (not shown). As it is necessary to form different material layers over the substrate 100 for fabrication processes, the different material layers are also formed on the alignment mark region. After a few fabrication processes on the device element region, a polysilicon layer 106 with a thickness of about 3000 .ANG. is formed over the substrate 100. There is a trench 107 also formed on the polysilicon layer 106, corresponding to the trench 104 shown in FIG. 1A.
In FIG. 1C, an isolating layer 108 with an original thickness of about 17000 .ANG. is formed over the polysilicon 106, in which the isolating layer 108 is employed for isolation in the device element region. Because the profile of the isolating layer 108 is usually not flat, a planarization process is performed to planarize the isolating layer 108. The isolating layer 108 has a thickness of about 10000 .ANG. at the trench 107 shown in FIG. 1B after planarization. At this stage, trench structure disappears on the exposed surface of the isolating layer 108. It is necessary to remove the isolating layer 108 due to device fabrication. After removing the isolating layer 108, a tungsten (W) layer 110 with a thickness of about 5000 .ANG. is formed over the substrate 100, as shown in FIG. 1D. The W layer 110 is for formation of W plug in the device element region. The exposed surface of the W layer 10 is not flat due to the under structure in the device element region and the trench 107 shown in FIG. 1B in the alignment mark region. A sharp dip also appears in the W layer 110 above the trench 107. A WCMP process is needed to planarize the W layer 110. In FIG. 1E, after the WCMP process, the W layer 110 becomes a W plug 110a filling the trench 107. Then a metal layer 112 with a thickness of about 5000 .ANG. is formed over the substrate 100. Since the W plug 110a has almost the same height as the height of the polysilicon layer 106 after the WCMP process, the alignment mark pattern 102 shown in FIG. 1A very nearly no longer exists on the exposed surface of the metal layer 106. This causes an alignment failure of the subsequent photo-mask.
FIGS. 2A-2E are cross-sectional views schematically illustrating another conventional fabrication flow of an alignment mark formed on the non-zero layer, according to a proposal from ASML company and Nikon company. A semiconductor substrate 200 includes an alignment mark region as shown in FIG. 2A and includes a device element region (not shown). As it is necessary to form different material layers over the substrate 200 for fabrication processes, the different material layers are also formed on the alignment mark region. In FIG. 2A, after a few fabrication processes on the device element region, a polysilicon layer 202 with a thickness of about 3000 .ANG. is formed over the substrate 200. In FIG. 2B, an oxide layer 204 serving as an isolating layer in the device element region is formed over the substrate 200 with an original thickness of about 17000 .ANG. and is planarized to have a thickness of about 10000 .ANG.. In FIG. 2C, in the alignment mark region 206, an opening 208 is formed by photolithography and etching. The opening 208 exposes the polysilicon layer 202 so that the depth of opening 208 is equal to the thickness of the oxide layer 204, about 10000 .ANG.. This is the step height of the alignment mark. In FIG. 2C and FIG. 2D, a W plug 210 is formed by filling the opening 208. In order to form the W plug 210, a W layer (not shown) is formed over the substrate 200. Then a WCMP process is performed to polish out the W layer above the oxide layer 204. The residual W layer is the W plug 210 filled into the opening 208 but not fully filled due to WCMP process. The concave structure of the W plug 210 allows the alignment mark pattern to be maintained but with poor quality of step height. In FIG. 2E, a metal layer 212 with a thickness of about 5000 .ANG. is formed over the substrate 200. The purpose of the metal layer 212 is to interconnect metal lines (not shown) in the device element region. The concave structure of the W plug 210 corresponding to the opening 208 shown in FIG. 2C also appears on the exposed surface of the metal layer 212. Here, it has even poorer step height, which is greatly reduced from the original step height of about 10000 .ANG.. Thus, a subsequent alignment of photo-mask becomes difficult because there is no sufficient step height available for an alignment sensor to respond with a correct signal. An alignment error is therefore inevitable.
The above two conventional methods are proposed to form alignment patterns. Since the W plug is included in device fabrication, it is necessary to perform a WCMP process to globally planarize the substrate but it reduces the step height of the alignment pattern. The profile of the alignment pattern is degraded or even fully smeared out. The insufficient step height of the alignment mark pattern causes the alignment sensor to produce a signal that is too weak and results in alignment error, or even causes photomask alignment to be impossible. All these tremendously affect the subsequent fabrication of the device.